Devices and integrated circuits are fabricated with multiple processing steps. Integrated circuits are often fabricated with one or more devices, which may include diodes, capacitors, and different varieties of transistors. These devices often have microscopic features that can only be manufactured with critical processing steps that require careful alignment of equipment used to build the devices.
Critical processing steps are used to fabricate device features having small dimensions, known as critical dimensions. Critical dimensions of a device often define the performance of the device and its surrounding circuitry. For example, gate length is a critical dimension of a field effect transistor and establishes, in part, the maximum operating frequency of the transistor.
If a critical processing step is not reproducible, the critical dimension cannot be repeatably obtained. Then, the performance of many devices and integrated circuits may not be acceptable. As a result, processing yields decrease and production costs increase. It is therefore desirable to enhance the latitude of processing steps, particularly critical processing steps.
A critical dimension can be measured at different stages of device and integrated circuit fabrication. Fabrication may include many successive steps. First, energy, such as light, is exposed through a mask onto a masking layer, such as resist. As shown in FIG. 1(a), during exposure (step 110), the critical dimension 101 can be measured as the length of the footprint of energy 103 incident on the masking layer 102. Any masking layer 102 having a minimum dose of energy 103 incident upon it is exposed. Then, the exposed masking layer is developed so that, for example, only unexposed masking layer 104 remains, as shown in FIG. 1(b). During development (step 120), the critical dimension 101 can be measured as the distance between unexposed masking layers 104, as shown in FIG. 1(b). Then, as shown in FIG. 1(c), material 105 not covered by the unexposed masking layer 104 is removed. The removal step (step 130) may be accomplished with etching. The material 105 may be a base layer, such as a semiconductor substrate or wafer. During removal (step 130), the critical dimension 101 can be measured as the distance between remaining material 105, as shown in FIG. 1(c). As an alternative to removal (step 140), a conductor 106 may be deposited between the unexposed masking layer 104 which is then removed, as shown in FIG. 1(d). The conductor 106 may form the gate of a transistor. The conductor 106 may be metal, doped polysilicon, or a combination thereof. During deposition (step 140), the critical dimension 101 can be measured as the length of the conductor 106.
Conventionally, enhanced processing latitude for critical dimensions are obtained by modifying the exposure (step 110). The exposure (step 110) is a critical processing step also known as lithography. Optical or photolithography involves patterning the masking layer 102 with energy from light. A photolithographic system 200 is illustrated in FIG. 2. Photolithography entails exposing light 203 through a mask 208 onto the masking layer 102. The masking layer 102 is formed on material 105, such as a base layer, described above.
The mask 208 is a tool used to construct a device or integrated circuit. The design of the mask is created by a human, a computer or both thereof. The mask 208 has a pattern 209 formed by a mask material 206, such as chrome, adjacent to a translucent material 205, such as quartz. Light 203 passes through the mask 208 where no mask material 206 is present. Typically, a lens 207 is placed between the mask 208 and the masking layer 102 to focus the light 203 onto the masking layer 102. The light 203 exposes the mask's pattern 209 onto the masking layer 102. The mask material 206 also defines a critical dimension 201 of the mask 208. The critical dimension 201 of the mask 208 corresponds to the critical dimensions 101, described above, on a wafer. However, the critical dimension 201 of the mask 208 may not be equivalent to the critical dimension 101 on the wafer. Often, the amount of mask material 206 defining the critical dimension 201 will be modified to enhance the latitude of the process steps used to fabricate wafer features having a critical dimension 101. Other parameters, such as mask material 206 width, exposure dose, and focus, can also be adjusted singly or in combination to achieve the critical dimension 101 on the wafer.
Conventionally, enhanced processing latitude for critical dimensions 101 are experimentally obtained by modifying process parameters. A series of test patterns is created. The test patterns are derived from the original pattern used to create structures having critical dimensions 101, but may have mask material edge positions varying about the original pattern defining the critical dimension 101. The test and original patterns are used to fabricate features using a matrix of processing parameters. The processing parameters may include photolithographic, resist development, and etch effect parameters. For example, the photolithographic parameters may include light exposure time and depth of focus of light. These processing parameters are known to persons skilled in the art.
Subsequently, one test pattern is chosen that demonstrates the least sensitivity to variations in process parameters. The chosen test pattern must form a feature with an accurate critical dimension 101 with specific process parameters. This procedure is laborious and expensive because it requires fabricating and analyzing multiple patterns formed with many different process parameters. Hence, only a finite amount of test patterns can practically be fabricated with different parameters. As a result of this constraint, process latitude can be enhanced to only a coarse extent. It is therefore desirable to more accurately and inexpensively enhance the latitude of the process parameters. This latitude is sometimes known as the contrast of the process. A high contrast indicates a high tolerance to process variation. A high contrast is desirable because a relatively large change in the process will induce a relatively small change of an edge position, possibly affecting a critical dimension 101, on a wafer.
Typically, the mask features are formed with distortion on a device or an integrated circuit as a result of nonlinear process effects. Nonlinear process effects occur during many processing steps, including exposure (step 110) and development (step 120). For example, distortion may occur during exposure (step 110) as a result of optical diffraction. Also, distortion may occur during development (step 120) as a result of resist swelling. Nonlinear processing effects are described in Silicon Processing for the VLSI Era by Wolf et al., which is herein incorporated by reference. The nonlinear processing effects can be analytically described with theoretical or empirical models. These models are known by persons skilled in the art. For example, optical nonlinear effects are described in Principles of Optics by Born et al., which is herein incorporated by reference. Such models may be used to simulate fabrication of a device or an integrated circuit in software, such as the FAIM program by Vector Technology (Brookline, Mass.), or programs from Precim Company (Portland, Oreg.).
Models may consist of one or more kernels, typically three-dimensional functions. When a model is convolved with a pattern, the behavior of that pattern at a specific point may be predicted. If many points are taken, a three-dimensional behavior can be predicted. A model threshold is a value that, when subtracted from the value of the model, can convert the modeled behavior to a binary behavior. For example, when a threshold of 0.3 is chosen, the model is convolved with the pattern and a value of 0.35 is returned. Subtracting 0.30 from 0.35 suggests that the pattern has a positive behavior at this point. Additionally, a shifted behavior can be used by retaining the calculated differential magnitude, e.g., 0.05. This information can be interpreted in any number of ways, depending on the specific application.
Conventionally, after process latitudes have been coarsely enhanced by experimentally choosing a test pattern and process parameters, the definition of features on the mask may be modified by proximity effect correction (PEC). Generally, PEC can be accomplished either manually using experimental data or using simulation software for feedback, or automatically with software using a rules-based method, or a model-based method. Examples of such software are Optimask from Vector Technology (Brookline, Mass.), Proteus from Precim Company (Portland, Oreg.), and OPRX from Trans Vector Technology (Camarillo, Calif.). Using a model-based method, the kernels are convolved with the original mask layout, compared to a threshold to determine the distortion, and a new mask pattern is created whose features will have diminished distortion when formed in an integrated circuit or device. The use of model-based PEC is well known to persons skilled in the art. The use of models to diminish distortions in fabricated features is further described in "Fast Sparse Aerial Image Calculation for OPC," 15th Annual Symposium on Photomask Technology and Management, 1995, by N. Cobb et al., and "Spatial Filter Models to Describe IC Lithographic Behavior," the Optical Microlithography SPIE 1997 Proceedings, Vol. 3051, pp. 469-478, by J. P. Stirniman et al., which are hereby incorporated by reference.
The specific process parameters determined by experiment, described previously, can be supplied to proximity effect correction software. To reduce cost and enhance accuracy, it is desirable to automatically transfer the process parameters to the proximity effect correction software.